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sdram_control
- 这是我从网上找到的用vhdl语言写的sdram控制器的代码。我的邮箱：wleechina@163.com-This is what I found online vhdl language used to write the sdram controller code. My mail : wleechina@163.com
lattice_sdram_source_code
- lattice sdram 控制器的源码，VHDL语言编码 包括仿真文件-lattice sdram controller source code, including VHDL simulation document coding
SDRAM_HY57V6416ET
- 现代的4bank*1M*16bit的SDRAM（HY57V6416ET）的VHDL行为仿真程序-modern 4bank 1M * * 16bit of SDRAM (HY57V6416ET) VHDL simulation program acts
VBuffer_1c6
- 视频采集并锁存到SDRAM中的完整代码，运行环境为QII，VHDL与标准参数宏模块调用混合设计 是学习视频采集的很好的参考-Video Capture SDRAM and latches to the integrity code, the operating environment for QII. VHDL standard parameter-called hybrid module is designed to study the Video Capture good reference
sdram_inf
- sdram操作的vhdl源代码，对自己编写SDRAM核有很好的参考意义
sdram_ctrl.tar
- SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。
SDRAMconntrol
- SDRAM控制器的设计与VHDL实现 是pdf格式的。在工程中实现过
t26a_ibis
- ddr sdram 的控制代码，采用VHDL语言书写
347
- SDRAM的控制器的VHDL语言编写代码
AlteraSdramIP
- Altera Sdram IP 源码，VHDL写的
sdRAM设计及源代码（vhdl）
- 通过对不读数据的不断刷新来保持数据，通过地址线复用来传输数据。
ddr_sdram_controller_vhdl.rar
- DDR SDRAM控制器的VHDL代码已经测试,DDR SDRAM controller VHDL code
sdramcontroller.rar
- FPGA读写SDRAM的VHDL程序(已经测试过),SDRAM read and write the VHDL program FPGA (already tested)
sdram_vhdl_lattice
- sdram接口的vhdl实现,适用于lattice的FPGA，内含状态机和各个模块的具体实现-SDRAM interface VHDL realization lattice applied to the FPGA, containing the state machine and the concrete realization of each module
pingpang
- 关于乒乓操作的，对于数据缓存有很大的用处-On the ping-pong operation of data cache for the great usefulness of
SDRAM_CTR
- vhdl语言编写的fpga控制sdram的程序，包括仿真结果.-program of vhdl to control sdram in which includes the simulating results
ctrller
- 本代码是控制SDRAM的VHDL代码，几经优化现已趋近完美，里面主要用状态机实现，现封装为entity，便于调用模块-This code is to control the SDRAM of the VHDL code, optimization has been several times closer to perfection, which is mainly used to achieve a state machine is encapsulated entity, easy to c
sdram_vhdl
- VHDL实现的读取和写入SDRAM的程序代码，学习的人可以参考下-VHDL implementation SDRAM read and write program code, can refer to the following study
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
pudn
- VHDL写的SDRAM的精简控制器。包含SDRAM接口控制器，和数据读写控制。含有实际抓取的signatap波形。为初学SDRAM者的，最好参考。-A SDRAM controller written in VHDL.Including SDRAM interface controller, read and write control. It is the best reference for SDRAM learners .